1. Field of the Invention
The present invention relates to a parallel processing shrinking key generator, and more particularly, to a shrinking key generator for providing a high speed key generation by configuring a parallel processing logic with a 2:1 multiplexer.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional shrinking key generator.
As show in FIG. 1, the conventional shrinking key generator includes a selection linear feedback shift register (LFSR) 1 for shifting a selection bit according to an inputted clock signal (Clock); a source LFSR 2 for shifting a source bit according to the clock signal (Clock); a sequential processing logic 3 having a multiplexer 31 for sequentially processing the selection bit of the selection LFSR 1 and the source bit of the source LFSR 2, and logic elements 32, 33; and an output amount register 4 for storing output bits of the sequential processing logic 3.
Hereinafter, operations of the conventional shrinking key generator of FIG. 1 will be explained in detail.
The conventional sequential processing logic 3 is easy to be implemented as hardware but a speed of generating key in the conventional sequential processing logic 3 is unusually slow. However, a parallel processing logic according to the present invention may be difficult to be embodied as hardware but quickly generates a key. A parallel processing logic is embodied as hardware by combining logical elements, such as AND gate or OR gate, based on a Boolean Algebraic characteristic of a parallel processing algorithm. That is, a combinational logic is used for embodying the parallel processing logic. In case of a shrinking key generator, a non-boolean algebraic key generation algorithm is used. Since the non-boolean algebraic key generation algorithm does not have the boolean algebraic characteristic, it is impossible to use a parallel processing logic for embodying the shrinking key generator as hardware up to now.
The shrinking key generator has been spotlighted as the most reliable algorithm for encoding/decoding data in a view of a security because there are no specific attacking methods reported or introduced. The shrinking key generator is generally selected when a high-speed key generation is not required. Although the shrinking key generator provides excellent reliability, the shrinking key generator is not selected for a system requiring an Mbps-level data processing speed because of slow speed of key generation. According to development of a wireless data link having wide-bandwidth and a fast Codec processing technology, a high-speed processing technology is also required for encoding and decoding data.
Conventionally, behavioral hardware description language (HDL) codes were not synthesized. According to development of a synthesis tool, many of Behavioral HDL codes, such as a conditional statement and a repetition statement, can be synthesized without problems. However, there are many difficulties still remained to synthesize Behavioral HDL codes, i.e., operation statements related to a pointer index, because of instabilities in an ineffective use of a Cell and a timing simulation. In order to express a selection logic of a shrinking key generator, operations related the pointer index and operations related to a dynamic memory assignment must be expressed as the Behavioral HDL codes by using the synthesis tool. Therefore, it is impossible to express the selection logic of the shrinking key generator having the non-boolean algebraic characteristic as HDL codes and to synthesize the HDL codes by using the synthesis tool.